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L6226
DMOS DUAL FULL BRIDGE DRIVER
s s s s s
s s s s s s
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V 2.8A OUTPUT PEAK CURRENT (1.4A DC) RDS(ON) 0.73 TYP. VALUE @ Tj = 25 C OPERATING FREQUENCY UP TO 100KHz PROGRAMMABLE HIGH SIDE OVERCURRENT DETECTION AND PROTECTION DIAGNOSTIC OUTPUT PARALLELED OPERATION CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN UNDER VOLTAGE LOCKOUT INTEGRATED FAST FREE WHEELING DIODES
PowerDIP24 (20+2+2)
PowerSO36
SO24 (20+2+2)
ORDERING NUMBERS: L6226N (PowerDIP24) L6226PD (PowerSO36) L6226D (SO24)
TYPICAL APPLICATIONS s BIPOLAR STEPPER MOTOR s DUAL OR QUAD DC MOTOR DESCRIPTION The L6226 is a DMOS Dual Full Bridge designed for motor control applications, realized in MultiPowerBLOCK DIAGRAM
BCD technology, which combines isolated DMOS Power Transistors with CMOS and bipolar circuits on the same chip. Available in PowerDIP24 (20+2+2), PowerSO36 and SO24 (20+2+2) packages, the L6226 features thermal shutdown and a non-dissipative overcurrent detection on the high side Power MOSFETs plus a diagnostic output that can be easily used to implement the overcurrent protection.
VBOOT
VBOOT VBOOT VBOOT CHARGE PUMP OVER CURRENT DETECTION 10V 10V
VSA
VCP PROGCLA OCDA
OCDA
OUT1A OUT2A
THERMAL PROTECTION ENA IN1A IN2A VOLTAGE REGULATOR OCDB OCDB PROGCLB ENB IN1B IN2B GATE LOGIC OVER CURRENT DETECTION 10V 5V GATE LOGIC
SENSEA
BRIDGE A
VSB
OUT1B OUT2B SENSEB BRIDGE B
D99IN1088A
September 2003
1/22
L6226
ABSOLUTE MAXIMUM RATINGS
Symbol VS VOD Parameter Supply Voltage Differential Voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Test conditions VSA = VSB = VS VSA = VSB = VS = 60V; VSENSEA = VSENSEB = GND Value 60 60 Unit V V
OCDA,OCDB OCD pins Voltage Range PROGCLA, PROGCLB VBOOT VIN,VEN VSENSEA, VSENSEB IS(peak) PROGCL pins Voltage Range Bootstrap Peak Voltage Input and Enable Voltage Range Voltage Range at pins SENSEA and SENSEB Pulsed Supply Current (for each VS pin), internally limited by the overcurrent protection RMS Supply Current (for each VS pin) Storage and Operating Temperature Range VSA = VSB = VS; tPULSE < 1ms VSA = VSB = VS VSA = VSB = VS
-0.3 to +10 -0.3 to +7 VS + 10 -0.3 to +7 -1 to +4 3.55
V V V V V A
IS Tstg, TOP
2.8 -40 to 150
A C
RECOMMENDED OPERATING CONDITIONS
Symbol VS VOD Parameter Supply Voltage Differential Voltage Between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Voltage Range at pins SENSEA and SENSEB RMS Output Current Operating Junction Temperature Switching Frequency -25 Test Conditions VSA = VSB = VS VSA = VSB = VS; VSENSEA = VSENSEB (pulsed tW < trr) (DC) -6 -1 MIN 8 MAX 52 52 Unit V V
VSENSEA, VSENSEB IOUT Tj fsw
6 1 1.4 +125 100
V V A C KHz
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L6226
THERMAL DATA
Symbol Rth-j-pins Rth-j-case Rth-j-amb1 Rth-j-amb1 Rth-j-amb1 Rth-j-amb2
(1) (2) (3) (4)
Description MaximumThermal Resistance Junction-Pins Maximum Thermal Resistance Junction-Case MaximumThermal Resistance Junction-Ambient
1
PowerDIP24 19 44 59
SO24 15 52 78
PowerSO36 2 36 16 63
Unit C/W C/W C/W C/W C/W C/W
Maximum Thermal Resistance Junction-Ambient 2 MaximumThermal Resistance Junction-Ambient 3 Maximum Thermal Resistance Junction-Ambient 4
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of 35 m). Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 m). Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 m), 16 via holes and a ground layer. Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.
PIN CONNECTIONS (Top View)
GND N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
D99IN1090A
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
GND N.C. N.C. VSB OUT2B N.C. VBOOT ENB PROGCLB IN2B IN1B SENSEB OCDB N.C. OUT1B N.C. N.C. GND
IN1A IN2A SENSEA OCDA OUT1A GND GND OUT1B OCDB SENSEB IN1B IN2B
1 2 3 4 5 6 7 8 9 10 11 12
D99IN1089A
24 23 22 21 20 19 18 17 16 15 14 13
PROGCLA ENA VCP OUT2A VSA GND GND VSB OUT2B VBOOT ENB PROGCLB
VSA OUT2A N.C. VCP ENA PROGCLA IN1A IN2A SENSEA OCDA N.C. OUT1A N.C. N.C. GND
PowerDIP24/SO24
PowerSO36(5)
(5) The slug is internally connected to pins 1,18,19 and 36 (GND pins).
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L6226
PIN DESCRIPTION
PACKAGE SO24/ PowerDIP24 PIN # 1 2 3 4 PowerSO36 PIN # 10 11 12 13 IN1A IN2A SENSEA OCDA Logic input Logic input Power Supply Open Drain Output Bridge A Logic Input 1. Bridge A Logic Input 2. Bridge A Source Pin. This pin must be connected to Power Ground directly or through a sensing power resistor. Bridge A Overcurrent Detection and thermal protection pin. An internal open drain transistor pulls to GND when overcurrent on bridge A is detected or in case of thermal protection. Bridge A Output 1. Signal Ground terminals. In Power DIP and SO packages, these pins are also used for heat dissipation toward the PCB. Bridge B Output 1. Bridge B Overcurrent Detection and thermal protection pin. An internal open drain transistor pulls to GND when overcurrent on bridge B is detected or in case of thermal protection. Bridge B Source Pin. This pin must be connected to Power Ground directly or through a sensing power resistor. Bridge B Input 1 Bridge B Input 2 Bridge B Overcurrent Level Programming. A resistor connected between this pin and Ground sets the programmable current limiting value for the bridge B. By connecting this pin to Ground the maximum current is set. This pin cannot be left non-connected. Bridge B Enable. LOW logic level switches OFF all Power MOSFETs of Bridge B. If not used, it has to be connected to +5V. Bootstrap Voltage needed for driving the upper Power MOSFETs of both Bridge A and Bridge B. Bridge B Output 2. Bridge B Power Supply Voltage. It must be connected to the supply voltage together with pin VSA. Bridge A Power Supply Voltage. It must be connected to the supply voltage together with pin VSB. Bridge A Output 2. Name Type Function
5 6, 7, 18, 19 8 9
15 1, 18, 19, 36 22 24
OUT1A GND
Power Output GND
OUT1B OCDB
Power Output Open Drain Output
10 11 12 13
25 26 27 28
SENSEB IN1B IN2B PROGCLB
Power Supply Logic Input Logic Input R Pin
14
29
ENB
Logic Input
15 16 17 20 21
30 32 33 4 5
VBOOT OUT2B VSB VSA OUT2A
Supply Voltage Power Output Power Supply Power Supply Power Output
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L6226
PIN DESCRIPTION (continued)
PACKAGE SO24/ PowerDIP24 PIN # 22 23 PowerSO36 PIN # 7 8 VCP ENA Output Logic Input Charge Pump Oscillator Output. Bridge A Enable. LOW logic level switches OFF all Power MOSFETs of Bridge A. If not used, it has to be connected to +5V. Bridge A Overcurrent Level Programming. A resistor connected between this pin and Ground sets the programmable current limiting value for the bridge A. By connecting this pin to Ground the maximum current is set. This pin cannot be left non-connected. Name Type Function
24
9
PROGCLA
R Pin
ELECTRICAL CHARACTERISTICS (Tamb = 25 C, Vs = 48V, unless otherwise specified)
Symbol Parameter Test Conditions Min 5.8 5 All Bridges OFF; Tj = -25C to 125C (6) Typ 6.3 5.5 5 Max 6.8 6 10 Unit V V mA C VSth(ON) Turn-on Threshold VSth(OFF) Turn-off Threshold IS Quiescent Supply Current
Tj(OFF)
Thermal Shutdown Temperature
165
Output DMOS Transistors RDS(ON) High-Side + Low-Side Switch ON Tj = 25 C Resistance Tj =125 C (6) Leakage Current EN = Low; OUT = VS EN = Low; OUT = GND Source Drain Diodes VSD trr tfr Forward ON Voltage Reverse Recovery Time Forward Recovery Time ISD = 2.8A, EN = LOW If = 1.4A 1.15 300 200 1.3 V ns ns -0.3 1.47 2.35 1.69 2.70 2 mA mA
IDSS
Logic Input VIL VIH IIL IIH Vth(ON) Low level logic input voltage High level logic input voltage Low Level Logic Input Current High Level Logic Input Current Turn-on Input Threshold GND Logic Input Voltage 7V Logic Input Voltage 1.8 -0.3 2 -10 10 2.0 0.8 7 V V A A V
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L6226
ELECTRICAL CHARACTERISTICS (continued) (Tamb = 25 C, Vs = 48V, unless otherwise specified)
Symbol Vth(OFF) Vth(HYS) Parameter Turn-off Input Threshold Input Threshold Hysteresis Test Conditions Min 0.8 0.25 Typ 1.3 0.5 Max Unit V V
Switching Characteristics tD(on)EN tD(on)IN tRISE tD(off)EN tD(off)IN tFALL tdt fCP Enable to out turn ON delay time (8) Input to out turn ON delay time Output rise time(8) ILOAD =1.4A, Resistive Load ILOAD =1.4A, Resistive Load (dead time included) ILOAD =1.4A, Resistive Load 40 500 500 40 0.5 -25CEnable to out turn OFF delay time (8) ILOAD =1.4A, Resistive Load Input to out turn OFF delay time Output Fall Time (8) Dead Time Protection Charge pump frequency ILOAD =1.4A, Resistive Load ILOAD =1.4A, Resistive Load
Over Current Detection Is over Input Supply Over Current DetectionThreshold -25CROPDR
Open Drain ON Resistance
tOCD(ON) OCD Turn-on Delay Time (8) tOCD(OFF) OCD Turn-off Delay Time (8)
(6) (7) (8)
Tested at 25C in a restricted range and guaranteed by characterization. See Fig. 1. See Fig. 2.
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L6226
Figure 1. Switching Characteristic Definition
EN
Vth(ON) Vth(OFF) t IOUT 90%
10%
D01IN1316
t tFALL tD(OFF)EN tD(ON)EN tRISE
Figure 2. Overcurrent Detection Timing Definition
IOUT OCD Threshold
t VOCD
90%
10% tOCD(ON) tOCD(OFF)
D01IN1222
t
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L6226
CIRCUIT DESCRIPTION POWER STAGES and CHARGE PUMP The L6226 integrates two independent Power MOS Full Bridges. Each Power MOS has an Rdson=0.73ohm (typical value @ 25C), with intrinsic fast freewheeling diode. Cross conduction protection is achieved using a dead time (td = 1s typical) between the switch off and switch on of two Power MOS in one leg of a bridge. Using N Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The Bootstrapped (Vboot) supply is obtained through an internal Oscillator and few external components to realize a charge pump circuit as shown in Figure 3. The oscillator output (VCP) is a square wave at 600kHz (typical) with 10V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table1. Table 1. Charge Pump External Components Values
CBOOT CP RP D1 D2 220nF 10nF 100 1N4148 1N4148
OPEN COLLECTOR OUTPUT
these pins. Two configurations are shown in Fig. 5 and Fig. 6. If driven by an open drain (collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Fig. 5. If the driver is a standard Push-Pull structure the resistor REN and the capacitor CEN are connected as shown in Fig. 6. The resistor REN should be chosen in the range from 2.2k to 180K. Recommended values for REN and CEN are respectively 100K and 5.6nF. More information on selecting the values is found in the Overcurrent Protection section. Figure 4. Logic Inputs Internal Structure
5V
ESD PROTECTION
D01IN1329
Figure 5. ENA and ENB Pins Open Collector Driving
5V REN OCDA or OCDB 5V
CEN
ENA or ENB
D02IN1355
Figure 3. Charge Pump Circuit
VS D1 D2 RP CP VCP VBOOT VSA VSB
D01IN1328
D02IN1356
Figure 6. ENA and ENB Pins Push-Pull Driving
OCDA or OCDB 5V REN ENA or ENB CEN
CBOOT
PUSH-PULL OUTPUT
LOGIC INPUTS Pins IN1A, IN2A, IN1B, IN2B, ENA and ENB are TTL/ CMOS and uC compatible logic inputs. The internal structure is shown in Fig. 4. Typical value for turn-on and turn-off thresholds are respectively Vthon=1.8V and Vthoff = 1.3V. Pins ENA and ENB are commonly used to implement Overcurrent and Thermal protection by connecting them respectively to the outputs OCDA and OCDB, which are open-drain outputs. If that type of connection is chosen, some care needs to be taken in driving
TRUTH TABLE
INPUTS EN L H H H H IN1 X L H L H IN2 X L L H H OUTPUTS OUT1 High Z GND Vs GND Vs OUT2 High Z GND GND Vs Vs
X High Z
= Don't care = High Impedance Output
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L6226
NON-DISSIPATIVE OVERCURRENT DETECTION AND PROTECTION In addition to the PWM current control, an overcurrent detection circuit (OCD) is integrated. This circuit can be used to provides protection against a short circuit to ground or between two phases of the bridge as well as a roughly regulation of the load current. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Fig. 7 shows a simplified schematic of the overcurrent detection circuit for the Bridge A. Bridge B is provided of an analogous circuit. To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current reaches the detection threshold Isover the OCD comparator signals a fault condition. When a fault condition is detected, an internal open drain MOS with a pull down capability of 4mA connected to OCD pin is turned on. Fig. 8 shows the OCD operation. This signal can be used to regulate the output current simply by connecting the OCD pin to EN pin and adding an external R-C as shown in Fig.7. The off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. IREF and, therefore, the output current detection threshold are selectable by RCL value, following the equations: - Isover = 2.8A 30% at -25C < T j < 125C if RCL = 0 (PROGCL connected to GND) 11050 - Isover = --------------- 10% at -25C < T j < 125C if 5K < RC < 40k R CL Fig. 9 shows the output current protection threshold versus RCL value in the range 5k to 40k. The Disable Time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN values and its magnitude is reported in Figure 10. The Delay Time tDELAY before turning off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 11. CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable Delay Time and the REN value should be chosen according to the desired Disable Time. The resistor REN should be chosen in the range from 2.2K to 180K. Recommended values for REN and CEN are respectively 100K and 5.6nF that allow obtaining 200s Disable Time.
9/22
L6226
Figure 7. Overcurrent Protection Simplified Schematic
OUT1A POWER SENSE 1 cell I1A POWER DMOS n cells I2A POWER DMOS n cells POWER SENSE 1 cell VSA OUT2A HIGH SIDE DMOSs OF THE BRIDGE A
C or LOGIC
TO GATE LOGIC
+
OCD COMPARATOR I1A / n I2A / n (I1A+I2A) / n
+5V RENA CENA OCDA RDS(ON) 40 TYP. ENA
INTERNAL OPEN-DRAIN OVER TEMPERATURE
IREF + 1.2V
IREF PROGCLA, RCLA.
D02IN1354
Figure 8. Overcurrent Protection Waveforms
IOUT ISOVER
VEN VDD Vth(ON) Vth(OFF) VEN(LOW)
ON OCD OFF ON BRIDGE OFF tOCD(ON) tEN(FALL) tD(OFF)EN tOCD(OFF) tEN(RISE) tD(ON)EN
D02IN1400
tDELAY
tDISABLE
10/22
L6226
Figure 9. Output Current Protection Threshold versus RCL Value
2 .5 2 .2 5 2 1 .7 5 1 .5 1 .2 5 1 0 .7 5 0 .5 0 .2 5 0
I SO V E R
[A ]
5k
10k
15k
20 k 2 5k R C L [ ]
30k
3 5k
40k
Figure 10. tDISABLE versus C EN and REN (VDD = 5V).
1 . 10
3
R EN = 220 k
R EN = 100 k
R EN = 47 k R EN = 33 k R EN = 10 k
tDISABLE [s]
100
10
1
1
10
100
C E N [nF]
11/22
L6226
Figure 11. tDELAY versus CEN (VDD = 5V).
10
tdelay [s]
1
0.1
1
10 Cen [nF]
100
THERMAL PROTECTION In addition to the Ovecurrent Detection, the L6226 integrates a Thermal Protection for preventing the device destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switch-off when the junction temperature reaches 165C (typ. value) with 15C hysteresis (typ. value).
12/22
L6226
APPLICATION INFORMATION A typical application using L6226 is shown in Fig. 12. Typical component values for the application are shown in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near the L6226 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the ENA/OCDA and ENB/OCDB nodes to ground set the shut down time for the Brgidge A and Bridge B respectively when an over current is detected (see Overcurrent Protection). The two current sources (SENSEA and SENSEB) should be connected to Power Ground with a trace length as short as possible in the layout. To increase noise immunity, unused logic pins are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and Signal Ground separated on PCB. Table 2. Component Values for Typical Application
C1 C2 CBOOT CP CENA CENB CREF 100uF 100nF 220nF 10nF 5.6nF 5.6nF 68nF D1 D2 RCLA RCLB RENA RENB RP 1N4148 1N4148 5K 5K 100k 100k 100
Figure 12. Typical Application
+ VS 8-52VDC VSA C1 C2 D1 VSB 20 17 OCDA ENA RENA ENA CENA RP D2 CP VBOOT SENSEA SENSEB LOADA OUT1A OUT2A LOADB OUT1B OUT2B 15 3 10 11 12 1 2 IN1B IN2B IN1A IN2A IN1B IN2B IN1A IN2A VCP 22 9 14 OCDB ENB RENB ENB CENB
4 23
POWER GROUND -
SIGNAL GROUND
CBOOT
5 21 8 16
GND GND GND GND
18 19 6 7
24
PROGCLA RCLA
13
PROGCLB RCLB
D02IN1344
13/22
L6226
PARALLELED OPERATION The outputs of the L6226 can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges. When the two halves of one full bridge (for example OUT1A and OUT2A) are connected in parallel, the peak current rating is not increased since the total current must still flow through one bond wire on the power supply or sense pin. In addition the over current detection senses the sum of the current in the upper devices of each bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detection threshold. For most applications the recommended configuration is Half Bridge 1 of Bridge A paralleled with the Half Bridge 1 of the Bridge B, and the same for the Half Bridges 2 as shown in Figure 13. The current in the two devices connected in parallel will share very well since the RDS(ON) of the devices on the same die is well matched. When connected in this configuration the over current detection circuit, which senses the current in each bridge (A and B), will sense the current in upper devices connected in parallel independently and the sense circuit with the lowest threshold will trip first. With the enables connected in parallel, the first detection of an over current in either upper DMOS device will turn of both bridges. Assuming that the two DMOS devices share the current equally, the resulting over current detection threshold will be twice the minimum threshold set by the resistors RCLA or RCLB in figure 13. It is recommended to use RCLA = RCLB. In this configuration the resulting Bridge has the following characteristics. - Equivalent Device: FULL BRIDGE - RDS(ON) 0.37 Typ. Value @ TJ = 25C - 2.8A max RMS Load Current - 5.6A max OCD Threshold Figure 13. Parallel connection for higher current
+ VS 8-52VDC VSA C1 C2 D1 VSB 20 17 9 14 RP D2 VCP CP VBOOT SENSEA SENSEB OUT1A OUT2A LOAD OUT1B OUT2B 15 3 10 5 21 8 16 18 19 6 7
D02IN1364
OCDB ENB
POWER GROUND -
22
4 23
OCDA ENA REN EN CEN IN1A IN2A
SIGNAL GROUND
CBOOT
1 2
IN1
11 12
IN1B IN2B IN2
24
PROGCLA RCLA
GND GND GND GND
13
PROGCLB RCLB
14/22
L6226
To operate the device in parallel and maintain a lower over current threshold, Half Bridge 1 and the Half Bridge 2 of the Bridge A can be connected in parallel and the same done for the Bridge B as shown in Figure 14. In this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense pins so the dissipation in the device will be reduced, but the peak current rating is not increased. When connected in this configuration the over current detection circuit, senses the sum of the current in upper devices connected in parallel. With the enables connected in parallel, an over current will turn of both bridges. Since the circuit senses the total current in the upper devices, the over current threshold is equal to the threshold set the resistor RCLA or RCLB in figure 14. RCLA sets the threshold when outputs OUT1A and OUT2A are high and resistor RCLB sets the threshold when outputs OUT1B and OUT2B are high. It is recommended to use RCLA = RCLB. In this configuration, the resulting bridge has the following characteristics. - Equivalent Device: FULL BRIDGE - RDS(ON) 0.37 Typ. Value @ TJ = 25C - 1.4A max RMS Load Current - 2.8A max OCD Threshold Figure 14. Parallel connection with lower Overcurrent Threshold
+ VS 8-52VDC VSA C1 C2 D1 VSB 20 17 4 23 RP D2 CP VBOOT SENSEA SENSEB OUT1A OUT2A LOAD OUT1B OUT2B 15 3 10 5 21 8 16 18 19 6 7
D02IN1361
OCDA ENA
POWER GROUND -
VCP
22
9 14
OCDB ENB REN EN CEN
SIGNAL GROUND
CBOOT
1 2
IN1A IN2A IN1B IN2B PROGCLA RCLA
INA
11 12
INB
24
GND GND GND GND
13
PROGCLB RCLB
15/22
L6226
It is also possible to parallel the four Half Bridges to obtain a simple Half Bridge as shown in Fig. 15. In this configuration the, the over current threshold is equal to twice the minimum threshold set by the resistors RCLA or RCLB in Figure 15. It is recommended to use RCLA = RCLB. The resulting half bridge has the following characteristics. - Equivalent Device: HALF BRIDGE - RDS(ON) 0.18 Typ. Value @ TJ = 25C - 2.8A max RMS Load Current - 5.6A max OCD Threshold Figure 15. Paralleling the four Half Bridges
+ VS 8-52VDC VSA C1 C2 D1 VSB 20 17 4 23 OCDA ENA
POWER GROUND -
RP D2 CP
VCP
22
9 14
OCDB ENB REN EN CEN
SIGNAL GROUND
CBOOT
VBOOT SENSEA SENSEB OUT1A OUT2A
15 3 10 5 21 1 2 IN1A IN2A IN1B IN2B PROGCLA
IN
LOAD OUT1B OUT2B GND GND GND GND
11 12
8 16 18 19 6 7
24
RCLA 13 PROGCLB RCLB
D02IN1365
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L6226
OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION In Fig. 16 and Fig. 17 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving two loads, for two different driving types: - One Full Bridge ON at a time (Fig.16) in which only one load at a time is energized. - Two Full Bridges ON at the same time (Fig.17) in which two loads at the same time are energized. For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125C maximum). Figure 16. IC Power Dissipation versus Output Current with One Full Bridge ON at a time.
ONE FULL BRIDGE ON AT A TIME
10 8
IA IB
I OUT
6
PD [W]
4 2 0
I OUT Test Conditions: Supply Voltage = 24V
0 0.25 0.5 0.75 1 1.25 1.5
No PW M fSW = 3 0 kHz (slow decay)
I OUT [A]
Figure 17. IC Power Dissipation versus Output Current with Two Full Bridges ON at the same time.
TWO FULL BRIDGES ON AT THE SAME TIME IA 10
8 6
I OUT
IB I OUT
PD [W ]
4 2 0
Test Conditions: Supply Volt age =24 V
0 0.25 0.5 0.75 1 1.25 1.5
I OUT [A ]
No PWM f SW = 30 kHz (slow decay)
THERMAL MANAGEMENT In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be deliver by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. Figures 19, 20 and 21 show the Junction-toAmbient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packages. For instance, using a PowerSO package with copper slug soldered on a 1.5 mm copper thickness FR4 board with 6cm2 dissipating footprint (copper thickness of 35m), the Rth j-amb is about 35C/W. Fig. 18 shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15C/W.
17/22
L6226
Figure 18. Mounting the PowerSO package.
Slug soldered to PCB with dissipating area
Slug soldered to PCB with dissipating area plus ground layer
Slug soldered to PCB with dissipating area plus ground layer contacted through via holes
Figure 19. PowerSO36 Junction-Ambient thermal resistance versus on-board copper area.
C / W
43
38
33
W ith o ut G ro u nd La yer
28
W ith Gro un d La yer W ith Gro un d La yer+ 16 via H o le s
23
18
On-Board Copper Area
13 1 2 3 4 5 6 7 8 9 10 11 12 13
s q. cm
Figure 20. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area.
C / W
49 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12
s q . cm
C o p pe r Are a is o n To p S i de C o p pe r Are a is o n Bo tto m S id e
On-Board Copper Area
Figure 21. SO24 Junction-Ambient thermal resistance versus on-board copper area.
C / W 68 66 64 62 60 58 56 54 52 50 48 1 2 3 4 5 6 7 8 9 10 11 12 s q. cm
C o pp er A re a is o n T op S id e
On-Board Copper Area
18/22
L6226
mm TYP. inch TYP.
DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S
MIN. 0.10 0 0.22 0.23 15.80 9.40 13.90
MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50
MIN. 0.004 0 0.008 0.009 0.622 0.370 0.547
MAX. 0.141 0.012 0.130 0.004 0.015 0.012 0.630 0.385 0.570
OUTLINE AND MECHANICAL DATA
0.65 11.05 10.90 5.80 2.90 0 15.50 0.80 11.10 0.429 2.90 6.20 0.228 3.20 0.114 0.10 0 15.90 0.610 1.10 1.10 0.031 10(max.) 8 (max.)
0.0256 0.435 0.437 0.114 0.244 0.126 0.004 0.626 0.043 0.043
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G".
N
N a2 A DETAIL A e3 H lead e A a1 E DETAIL A
c DETAIL B
D a3
36 19
slug BOTTOM VIEW E3
B E2 E1 DETAIL B
0.35 Gage Plane
D1
1
1
8
-C-
S h x 45 b
0.12
M
L
SEATING PLANE G C
AB
PSO36MEC
(COPLANARITY)
19/22
L6226
mm MIN. A A1 A2 B B1 c D E e E1 e1 L M 3.180 6.350 0.410 1.400 0.200 31.62 7.620 2.54 6.600 7.620 3.430 0.125 6.860 0.250 0.380 3.300 0.460 1.520 0.250 31.75 0.510 1.650 0.300 31.88 8.260 0.016 0.055 0.008 1.245 0.300 0.100 0.260 0.300 0.270 TYP. MAX. 4.320 0.015 0.130 0.018 0.060 0.010 1.250 0.020 0.065 0.012 1.255 0.325 MIN. inch TYP. MAX. 0.170
DIM.
OUTLINE AND MECHANICAL DATA
0.135
Powerdip 24
0 min, 15 max.
E1
A2
A
L
A1
B
B1
e
e1
D
24
13 c
1
12 M
SDIP24L
20/22
L6226
mm DIM. MIN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 15.20 7.40 1.27 10.65 0;75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 15.60 7.60 MIN. 0.093 0.004 0.013 0.009 0.598 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.200 0.013 0.614 0.299 Weight: 0.60gr inch
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO24
0070769 C
21/22
L6226
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
22/22

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